My ADEPT Blog

Spartan6 DSP48 View

2011-11-30T06:25:00.001-05:00

Spartan6 DSP48 View (see the first snapshot below. Click on it for full resolution) in ADEPT can be displayed after an NCD is read with "Get DSP48 attributes" checked (see the second snapshot below). The DSP48 view displays all DSP48 instances in the design with their placements, major attributes and decoded functions. If OPMODE inputs are not connected to constant 1's or 0's, their values will have "?" in them. If OPMODE can't be decoded, the corresponding decoding columns will be blank.

Please check Spartan-6 FPGA DSP48A1 Slice User Guide for details on DSP48A1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

Virtex6 Clock Region View

2011-10-10T23:04:00.000-04:00

The ADEPT Virtex6 clock region view (click on the snapshot below to see the full size picture) displays the clock region map with detailedinformation (clocking components, clock utilization, etc) about each clockregion. The “CR” column shows the clock region XmYn coordinates. Thenumber of used and total global clocks in a clock region is displayed in G:used/total format for each clockregion. If the number of used clocks exceeds the total global clocks in a clock region, it will be highlighted in red. This view also shows MMCMs, BUFGs, BUFIOs, BUFRs and MGTs in each clock region.

Virtex6 IO Bank View

2011-09-22T06:49:00.001-04:00

The View->IO Bank View in ADEPT displays all IO banks in IO columns with VCCO and DCI settings for each bank. It also prints a warning message at the end of the table that bitgen must be run with the .pcf file.

Depending on the device, there may be 3 or 4 IO columns displayed. The column header indicates the IO column an IO bank is in:

OL = Outer Left
CL = Center Left
CR = Center Right
OR = Outer Right

The snapshot below shows the IO Bank View for a Virtex6 device.

Spartan6 Pin Table View Enhancements in v0.44.2

2011-07-31T14:14:00.001-04:00

ADEPT v0.44.2 includes several enhancements to the Spartan6 Pin Table View:

The flight time for Spartan6 devices can be also calculated from data in IBIS models. Follow the instructions on the blog: Calculate IO flight time using IBIS model (Of course, download Spartan6 IBIS models instead)
Two new columns, IN_TERM and OUT_TERM, are added to display the IN_TERM and OUT_TERM constraints for Spartan6 IOs. Together with the "DIFF_TERM" column, the S6 pin table view now covers all IO termination configurations. These three columns can be populated by

constraints in a UCF (File->Read UCF menu) or
configurations in a NCD file (Read NCD with "Get Pin assignments/attributes" checked)

Below is the snpashot of the new Spartan6 Pin Table View

Make Part Compatible for 7 Series FPGAs

2011-05-21T13:49:00.000-04:00

Several new things introduced in 7 Series FPGAs make part migration trickier than previous familiies:

Parts are available in new package types FBG, FHG and FLG in addition to the FFG package. Different package types with the same package pin count may be compatible.
Stacked Silicon Interconnect (SSI ) devices have multiple FPGA dies on the same package substrate. Each die is designated as a Super Logic Region (SLR) in the device view. It's recommended not to assign IOs of the same interface across SLR boundary.
Some 7 Series devices have two types of IO banks: High Range (HR) banks (max 3.3V VCCO, no ODELAY) and High Performance (HP) banks (max 1.8V VCCO). Depending on the design, IOs with the same IO name but different bank types in two different part may not be compatible.

ADEPT 0.43.6 added enhancements below to the "ADEPT Tools->Make Part Compatible" function to point out the changes above and hopefully make the migration planning easier:

All parts with the same package pin count can be selected as the new device. In this example, parts in FFG1761, FLG1761, FHG1761 packages are listed in the "New Device" drop-down list.
If the current device and/or the new device are SSI part, the SLR boundary is highlighted in yellow in-between two banks for bonded IOs in different SLRs
For IOs in a HR bank, the suffix "_HR" is appended to all IO names in that bank.

Show Footprint in Excel

2011-04-20T01:18:00.001-04:00

The Excel->Show Footprint in Excel function displays the footprint of the selected device in Excel spreadsheet. Below is a snapshot of the exported spreadsheet (download example here). Key features:

Pads are color-coded based on pad types (GND, VCCO, MGT, etc) and IO banks.
If a UCF or CSV file with pin locations is read in ADEPT, the signal names are displayed on the pads they are assigned to. For example, if the signal ddr3_dq[9] is LOC'ed to A6, the signal name is displayed on the pad A6 in the spreadsheet (the cell with a red square below). Unused IO pads have the string "IO" and the IO name on them.

Calculate IO flight time using IBIS model

2010-11-03T22:09:00.000-04:00

Some high speed interfaces (DDR3 memory interface for example) require skew of signals in the interface well matched. One of the factors affecting the skew is the flight time from the IO pad on the die to the package pin. AR15321 provides a simple method of multiplying the package trace length by 6.0ps/mm(best case) or 7.1ps/mm(worst case) to calculate the flight time. This is the formula that ADEPT has been using for a long time. A new AR (AR34174) was published recently with instructions on how to use the inductance and capacitance matrix in IBIS model to get more precise flight time. ADEPT v0.42.1 incorporated the new method to calculate the flight time for all Virtex6 devices/packages. Below are instructions on how to use the new method:

Download Virtex6 IBIS models from Xilinx download center

Unzip the IBIS Models zip file and you will see lots of .pkg files for different package/device combinations
Run ADEPT and load a Virtex6 device/package
Run "File->Read IBIS Model" to load the IBIS model .pkg file for the loaded device
Once the IBIS model is read in, the "Trace Len" column is now displayed as "Flight Time LC" column to indicate that the flight time (ps) is calculated with the inductance(L) and capacitance(C) data extracted from the IBIS model

Enable Macro in Excel 2007 for "Export to Excel" functions

2010-05-19T13:13:00.000-04:00

Excel 2007 doesn't automatically pop up a window asking user to enable macros. Instead, it silently displays a security warning message right below the tool bar (see the snapshotshot). If you don't notice it, ADEPT may appear to be doing nothing when you run any "Export to Excel" function. You will need to click the "Options..." button in the warning message and a window will pop up for you to enable the macro. Select "Enable this content" and then click OK. The exported spreadsheet will then be generated.

Run ADEPT with IDS 12.1

2010-05-04T23:21:00.005-04:00

IDS 12.1 installer doesn't set up environment variables such as XILINX and add paths to IDS tools to the PATH environment variable. Instead all IDS tools now execute settings32.bat in the installation directory first to set up the environment before invoking the actual executable. This makes it a lot easier to keep multiple IDS versions on the same machine.

However, ADEPT uses the PATH environment variable to find IDS command line tools. This means that you would have to modify PATH manually to run ADEPT with IDS 12.1. To make things easier, ADEPT 0.40.0 now includes a shortcut "adept_ise12.bat" that uses IDS 12.1 settings32.bat to set up the environment before starting ADEPT. You can just double-click on this shortcut to run ADEPT with IDS 12.1. The target of the shortcut (see the snapshot below) is currently set to the default installation path used by IDS 12.1 installer. If you installed 12.1 in a different location, please change the path to settings32.bat to match your IDS 12.1 installation directory. After you made the change, make sure you rename the file so it won't get overwritten if you install a new ADEPT release in the same directory next time.

Component View displays BRAM modes for Virtex6

2010-04-06T23:26:00.002-04:00

According to AR34859 (http://www.xilinx.com/support/answers/34859.htm), Virtex6 BRAM can become corrupted with different clocks clocking CLKA and CLKB of the block RAM and address overlap in the modes below

True Dual Port (TDP) mode with WRITE_MODE = READ_FIRST for the RAMB36E1 or RAMB18E1 components
Simple Dual Port (SDP) mode for the RAMB36E1 or RAMB18E1 components, including the Error Correction Code (ECC) implementation

To help identify potential problems with BRAM corruption, the "View->Component View" in ADEPT 0.39.7 now displays the modes for all BRAMs used in the design (see the snapshot below). When you read a NCD, make sure "Get instance names/MGT attributes" checkbox is checked. BRAMs in READ_FIRST mode are highlighted in red. Please note that ADEPT currently does NOT check if CLKA and CLKB are different clocks.

Spartan6 Clock Region View

2010-02-02T23:18:00.004-05:00

The Spartan6 Clock Region View displays which BUFH/BUFG/DCM/PLL is in which clock region. The CR column shows the clock region XY coordinates. e.g. X0Y6 is CLOCK_REGION_X0Y6. An example Excel spreadsheet can be downloaded here.

Logic Utilization View

2009-12-28T20:05:00.002-05:00

The "View->Logic Utilization View" displays the hierarchical logic utilization of a design after the NCD is read with "Get logic utilization" checked. It also displays the total logic resources in the device and utilization % for each resource category. Click "+/-" in front of "Expand/Collapse all" to expand/collapse all hierarchies. Click "+/-" on each row to expand/collapse the hierarchy for that row.

The "Logic Utilization View" can be exported to an Excel spreadsheet (Excel->Show Logic Utilization in Excel function).

Spartan6 GCLK View in Excel

2009-12-17T19:37:00.004-05:00

ADEPT v0.38.9 added a new function "Excel->Show Spartan6 GCLK in Excel" that displays GCLK pads, their pin numbers/signal names and BUFGs they can drive in an Excel spreadsheet. The snapshot is shown below. An example .xls file can be downloaded here.

Virtex5 Component View

2009-12-14T21:26:00.012-05:00

The Virtex5 Component View (View->Component View menu) has two parts:

The first part displays all DCM, PLL, BUFGCTRL and global clock pad (GC_P pins) in the order as they are on the device. It also highlights an important clocking rule (circled in the snapshot below) that the global clock pad can only drive BUFG/DCM/PLL in the same top or bottom half. The clocking components above the note are in the top half and the clock components below the note are in the bottom half.

The second part displays BUFIO, BUFR, DSP48, BRAMB, and RPMs used in the design when an NCD is read in (File->Read NCD File) wtih "Get Instance Names" checked (see the snapshot below):

The Component View can be exported to an Excel spreadsheet (Excel->Show Component in Excel menu). The placements of all instances can be exported to a UCF (File->Export Instance LOC to UCF).

Virtex6 DSP48 View

2009-12-10T22:46:00.001-05:00

Compared to the Virtex5 DSP48 View in ADEPT, the Virtex6 DSP48 View has 5 new columns (circled in the snapshot below) for the new pre-adder in DSP48E1 slice. The INMODE4, INMODE3:0 and USE_DPORT columns display the actual values for the INMODE input and USE_DPORT attribute. The MULT_A and MULT_B columns display inputs to the multiplier A and B ports based on the decoding of INMODE and USE_DPORT.

Please check Virtex-6 FPGA DSP48E1 Slice User Guide for details on DSP48E1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

DSP48 View - Virtex5

2009-11-21T06:38:00.019-05:00

ADEPT v0.38.6 added a new "View->DSP48 View" function for Virtex5. After an NCD is read with "Get DSP48 attributes" checked (see the snapshot at the end), the DSP48 view displays all DSP48 instances in the design with their placements (Comp Name column), OPMODE and ALUMODE values (OPMODE and ALUMODE columns) and their decodings (X, Y, Z and ALU OP columns), and pipeline register attributes (A/B/C/M/PREG columns). If OPMODE or ALUMODE are not connected to constant 1's or 0's, their values will have "?" in them. If OPMODE or ALUMODE can't be decoded, the corresponding decoding columns will be blank.

Please check Virtex-5 FPGA XtremeDSP Design Considerations User Guide for details on DSP48E operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

Special Pin Setup Window

2009-11-11T21:08:00.003-05:00

ADEPT 0.38.x has a new function "Tools->Special Pin Setup". This function displays information (tie high/low, types and important notes) for special purpose pins such as configuration pins, power pins, etc. A snapshot of this new function is shown below:

1. Pop-up window to select configuration mode, data width, configuration clk frequency and power supply ramp time.

Review: display the special pin setup information for the selected mode/width
Example: open the list of links for all configuration examples in your web browser
Write UCF: write "PROHIBIT" constraints for dual-purpose pins to UCF

2. Current configuration mode/width, bitstream size, config clk frequency, power supply ramp time and total configuration time
3. Values of Mode pins M[2:0] for current configuration mode
4. Important notes on some configurations pins
5. Pins requiring special attention highlighted in red

Find IDELAYCTRL locations

2009-11-09T00:14:00.074-05:00

ADEPT can be used to easily find IDELAYCTRLs in each IO column in a clock region. For Virtex5, Virtex6 or Virtex-7/Kintex-7, an IO column in a clock region is the same as an IO bank.

Load the target device in ADEPT. The Pin table view is displayed.
Run View->Display IDELAYCTRL, which shows the IDELAYCTRL_XmYn in the center of each IO column in a clock region.
Run File->Read UCF to load pin locations. If any IO in an IO column of a clock region uses IDELAY or IODELAY in FIXED, VARIABLE, or VAR_LOADABLE mode, the IDELAYCTRL in that IO column/clock region needs to be used by manual instantiation or automatic replication in MAP.
Optionally if a NCD is read in from File->Read NCD, the tool will display IDELAY or IODELAY modes in the Notes column for IOs using IDELAYs or IODELAYs and the instance names for all used IDELAYCTRLs.

Below is a snapshot of the GUI after an NCD is read in.Click on it to see the full image.

The clock region XY is displayed in the first row of each clock region in the SLCR column.
The Notes column shows the modes of IDELAY or IODELAY for all applicable IOs.
IDELAYCTRL_XmYn is in the center of the clock region.
IO bank number is shown in the Bank column. In this particular case, each IO bank is one clock region tall.

Virtex5 IO Bank View

2009-10-15T22:59:00.006-04:00

The View->IO Bank View displays all IO banks in IO columns with VCCO and DCI settings for each bank. v0.38.4 and newer also prints a warning message at the end of table that bitgen must be run with the .pcf file.

Depending on the device, there may be 3 or 4 IO columns displayed. The column header indicates the IO column an IO bank is in:

OL = Outer Left
CL = Center Left
CR = Center Right
OR = Outer Right

The snapshot below shows the IO Bank View for a Virtex5 device.

Make Part Compatible

2009-09-25T00:10:00.004-04:00

[Update May 21, 2011: click here for additional information about Make Part Compatible function for 7 Series FPGAs]
The "Tools->Make Part Compatible" function checks the pin compatibility between current selected part and a new device in the same package. The tool creates a spreadsheet that lists all pins from both parts side by side and highlights incompatible pins in red. The “PROHIBIT” column for all incompatible pins are set to yes (“Y”). Once the spreadsheet is reviewed, users can write out a UCF file with PROHIBIT constraints added for all incompatible user IOs.

Generate Orcad Symbol

2009-09-24T00:00:00.003-04:00

ADEPT can export a CSV file that can be directly copied and pasted to Orcad Capture part generation spreadsheet to generate a multi-part symbol for the selected device.

Orcad 10.5 or newer is required because the "New Part from Spreadsheet" function was first added to version 10.5. For users with older versions of Orcad, the "Tools->Generate Part" function in Orcad should still work(http://www.orcad.com/documents/community.faqs/capture/cap03022.aspx) with simple changes to the CSV file exported in ADEPT.

Run ADEPT
Load target device
Run "File->Export CSV for Orcad Symbol" to export all pins (user I/Os, configuration pins, power pins, etc) to a csv file (say orcad_symbol.csv) that has the same columns as the Orcad symbol spreadsheet
Open the csv file orcad_symbol.csv in MS Excel. Scroll down to the last row and take note of the section number (the last column). The section number is the number of parts that will be generated for the device
Run Orcad Capture and select "New Part From Spreadsheet". On the "New Part Creation Spreadsheet" window, enter a part name in "Part Name" box, the section number above in the "No. of Sections" box, and select "Numeric" for "Part Numbering". This step MUST be done first for the section numbers to show up correctly for each pin.
Go back to MS Excel and select rows 7 to the last row and columns A to G. Press CTRL-C to copy the selection to clipboard.
Switch to Orcad Capture "New Part Creation Spreadsheet" window and select the first cell in the spreadsheet. Press CTRL-V to paste the clipboard content to the spreadsheet. Click "Save" to save the part. You now have a Orcad symbol with multiple parts: one part per bank (including bank 0 and MGT banks), one part for VCC*, one part for GND.