New Columns on 7 Series Pin Table View

The 7 series Pin Table View in ADEPT has several new columns displaying new features only available in 7 series FPGAs:

• SLR: Super Logic Region number for SSI (Stacked Silicon Interconnect) devices.
• ByteGrp: memory byte group number. e.g. for DDR3 interface, DQS and associated DQ pins need to be placed in the same byte group.
• Min/Max Dly ps: minimum/maximum flight time in pico second. These numbers directly come from the device package file and correlate well with calculations using IBIS models.

Spartan6 DSP48 View

Spartan6 DSP48 View (see the first snapshot below. Click on it for full resolution) in ADEPT can be displayed after an NCD is read with "Get DSP48 attributes" checked (see the second snapshot below). The DSP48 view displays all DSP48 instances in the design with their placements, major attributes and decoded functions. If OPMODE inputs are not connected to constant 1's or 0's, their values will have "?" in them. If OPMODE can't be decoded, the corresponding decoding columns will be blank.

Please check Spartan-6 FPGA DSP48A1 Slice User Guide for details on DSP48A1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.