Please check Spartan-6 FPGA DSP48A1 Slice User Guide for details on DSP48A1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.
My ADEPT Blog
Notes and tips & tricks on ADEPT for Xilinx FPGA
Wednesday, November 30, 2011
Spartan6 DSP48 View
Spartan6 DSP48 View (see the first snapshot below. Click on it for full resolution) in ADEPT can be displayed after an NCD is read with "Get DSP48 attributes" checked (see the second
snapshot below). The DSP48 view displays all DSP48 instances in the
design with their placements, major attributes and decoded functions. If OPMODE inputs are not connected to constant 1's or 0's, their
values will have "?" in them. If OPMODE can't be decoded, the
corresponding decoding columns will be blank.
Monday, October 10, 2011
Virtex6 Clock Region View
The ADEPT Virtex6 clock region view (click on the snapshot below to see the full size picture) displays the clock region map with detailed
information (clocking components, clock utilization, etc) about each clock
region. The “CR” column shows the clock region XmYn coordinates. The
number of used and total global clocks in a clock region is displayed in G:used/total format for each clock
region. If the number of used clocks exceeds the total global clocks in a clock region, it will be highlighted in red. This view also shows MMCMs, BUFGs, BUFIOs, BUFRs and MGTs in each clock region.
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