Logic Utilization View

The "View->Logic Utilization View" displays the hierarchical logic utilization of a design after the NCD is read with "Get logic utilization" checked. It also displays the total logic resources in the device and utilization % for each resource category. Click "+/-" in front of "Expand/Collapse all" to expand/collapse all hierarchies. Click "+/-" on each row to expand/collapse the hierarchy for that row.

The "Logic Utilization View" can be exported to an Excel spreadsheet (Excel->Show Logic Utilization in Excel function).

Spartan6 GCLK View in Excel

ADEPT v0.38.9 added a new function "Excel->Show Spartan6 GCLK in Excel" that displays GCLK pads, their pin numbers/signal names and BUFGs they can drive in an Excel spreadsheet. The snapshot is shown below. An example .xls file can be downloaded here.

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Virtex5 Component View

The Virtex5 Component View (View->Component View menu) has two parts:

The first part displays all DCM, PLL, BUFGCTRL and global clock pad (GC_P pins) in the order as they are on the device. It also highlights an important clocking rule (circled in the snapshot below) that the global clock pad can only drive BUFG/DCM/PLL in the same top or bottom half. The clocking components above the note are in the top half and the clock components below the note are in the bottom half.

The second part displays BUFIO, BUFR, DSP48, BRAMB, and RPMs used in the design when an NCD is read in (File->Read NCD File) wtih "Get Instance Names" checked (see the snapshot below):

The Component View can be exported to an Excel spreadsheet (Excel->Show Component in Excel menu). The placements of all instances can be exported to a UCF (File->Export Instance LOC to UCF).

Virtex6 DSP48 View

Compared to the Virtex5 DSP48 View in ADEPT, the Virtex6 DSP48 View has 5 new columns (circled in the snapshot below) for the new pre-adder in DSP48E1 slice. The INMODE4, INMODE3:0 and USE_DPORT columns display the actual values for the INMODE input and USE_DPORT attribute. The MULT_A and MULT_B columns display inputs to the multiplier A and B ports based on the decoding of INMODE and USE_DPORT.

Please check Virtex-6 FPGA DSP48E1 Slice User Guide for details on DSP48E1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.