Component View displays BRAM modes for Virtex6

According to AR34859 (http://www.xilinx.com/support/answers/34859.htm), Virtex6 BRAM can become corrupted with different clocks clocking CLKA and CLKB of the block RAM and address overlap in the modes below

• True Dual Port (TDP) mode with WRITE_MODE = READ_FIRST for the RAMB36E1 or RAMB18E1 components
• Simple Dual Port (SDP) mode for the RAMB36E1 or RAMB18E1 components, including the Error Correction Code (ECC) implementation

 To help identify potential problems with BRAM corruption, the "View->Component View" in ADEPT 0.39.7 now displays the modes for all BRAMs used in the design (see the snapshot below). When you read a NCD, make sure "Get instance names/MGT attributes" checkbox is checked. BRAMs in READ_FIRST mode are highlighted in red. Please note that ADEPT currently does NOT check if CLKA and CLKB are different clocks.