DSP48 View - Virtex5

ADEPT v0.38.6 added a new "View->DSP48 View" function for Virtex5. After an NCD is read with "Get DSP48 attributes" checked (see the snapshot at the end), the DSP48 view displays all DSP48 instances in the design with their placements (Comp Name column), OPMODE and ALUMODE values (OPMODE and ALUMODE columns) and their decodings (X, Y, Z and ALU OP columns), and pipeline register attributes (A/B/C/M/PREG columns). If OPMODE or ALUMODE are not connected to constant 1's or 0's, their values will have "?" in them. If OPMODE or ALUMODE can't be decoded, the corresponding decoding columns will be blank.

Please check Virtex-5 FPGA XtremeDSP Design Considerations User Guide for details on DSP48E operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

Special Pin Setup Window

ADEPT 0.38.x has a new function "Tools->Special Pin Setup". This function displays information (tie high/low, types and important notes) for special purpose pins such as configuration pins, power pins, etc. A snapshot of this new function is shown below:

1. Pop-up window to select configuration mode, data width, configuration clk frequency and power supply ramp time.

• Review: display the special pin setup information for the selected mode/width
• Example: open the list of links for all configuration examples in your web browser
  
• Write UCF: write "PROHIBIT" constraints for dual-purpose pins to UCF
  

2. Current configuration mode/width, bitstream size, config clk frequency, power supply ramp time and total configuration time
3. Values of Mode pins M[2:0] for current configuration mode
4. Important notes on some configurations pins
5. Pins requiring special attention highlighted in red

Find IDELAYCTRL locations

ADEPT can be used to easily find IDELAYCTRLs in each IO column in a clock region. For Virtex5, Virtex6 or Virtex-7/Kintex-7, an IO column in a clock region is the same as an IO bank.

• Load the target device in ADEPT. The Pin table view is displayed.
• Run View->Display IDELAYCTRL, which shows the IDELAYCTRL_XmYn in the center of each IO column in a clock region.
• Run File->Read UCF to load pin locations. If any IO in an IO column of a clock region uses IDELAY or IODELAY in FIXED, VARIABLE, or VAR_LOADABLE mode, the IDELAYCTRL in that IO column/clock region needs to be used by manual instantiation or automatic replication in MAP.
• Optionally if a NCD is read in from File->Read NCD, the tool will display IDELAY or IODELAY modes in the Notes column for IOs using IDELAYs or IODELAYs and the instance names for all used IDELAYCTRLs.

Below is a snapshot of the GUI after an NCD is read in.Click on it to see the full image.

• The clock region XY is displayed in the first row of each clock region in the SLCR column.
• The Notes column shows the modes of IDELAY or IODELAY for all applicable IOs.
• IDELAYCTRL_XmYn is in the center of the clock region.
• IO bank number is shown in the Bank column. In this particular case, each IO bank is one clock region tall.