ADEPT can be used to easily find IDELAYCTRLs in each IO column in a clock region. For Virtex5, Virtex6 or Virtex-7/Kintex-7, an IO column in a clock region is the same as an IO bank.
- Load the target device in ADEPT. The Pin table view is displayed.
- Run View->Display IDELAYCTRL, which shows the IDELAYCTRL_XmYn in the center of each IO column in a clock region.
- Run File->Read UCF to load pin locations. If any IO in an IO column of a clock region uses IDELAY or IODELAY in FIXED, VARIABLE, or VAR_LOADABLE mode, the IDELAYCTRL in that IO column/clock region needs to be used by manual instantiation or automatic replication in MAP.
- Optionally if a NCD is read in from File->Read NCD, the tool will display IDELAY or IODELAY modes in the Notes column for IOs using IDELAYs or IODELAYs and the instance names for all used IDELAYCTRLs.
- The clock region XY is displayed in the first row of each clock region in the SLCR column.
- The Notes column shows the modes of IDELAY or IODELAY for all applicable IOs.
- IDELAYCTRL_XmYn is in the center of the clock region.
- IO bank number is shown in the Bank column. In this particular case, each IO bank is one clock region tall.
One problem of working with IDELAYCTRL is figuring out which ones to use. There are several rules of using IDELAYCTRL, which are not always easy to follow. Especially when a design contains cores, such as memory controller, Ethernet MAC, which already have instantiated IDELAYCTRL, and user logic. I found that the fastest way is to explicitly instantiating all IDELAYCTRL primitives in a chip, building a design, and then removing those that unused.
ReplyDeleteThanks,
Evgeni
Thanks for sharing the tip. With your approach you will still need to find out which IDELAYCTRL's are unused after the implementation is done. This is where ADEPT comes in handy:
ReplyDelete* Read in NCD
* Find all IDELAYCTRL's in regions that have no IOs with IODELAY=FIXED or VARIABLE or VAR_LOADABLE
I am also facing same problem. Please help me. I have cascaded two IDELAYCTRL modules to increase the tap delays. Picture is attached for reference.
ReplyDeleteI have four IDELAYCTRL Groups, named as:
1. Ethernet
2. Memory Integrator Group MIG0
3.Pre-Delay IDELAYCTRL Module
4.POst-Delay IDELAYCTRL Module (mb_subsystem_i/RX_deSERIALIZER)
1. At first i got error PLIDC-4 for IDELYCTRL IODELAYS of MIG0 and mb_subsystem_i/RX_deSERIALIZER was conflicting groups with IO bank 34. This problem was resolved with the help of Xilinx Moderator @syedz. He guided me to add the command to XDC. The implementation was successful. But this cascaded module didnt work.
2. Then i saw in the IDELAYCTRL list, there was no mb_subsystem_i/RX_deSERIALIZER IDELAYCTRL group. For that defining, i add another command in XDC to put it in IODELAY Group and assign it a new location:
set_property IODELAY_GROUP GRP_IODELAY0 [get_cells mb_subsystem_i/RX_deSERIALIZER/inst/pins[0].idelaye2_bus]
set_property LOC IDELAYCTRL_X0Y0 [get_cells mb_subsystem_i/RX_deSERIALIZER/inst/delayctrl]
But i now, i get another error with PLIDC-4: [DRC PLIDC-1] IDELAYCTRL missing from group with assigned IODELAYs: IODELAY cells have been found to be associated with IODELAY_GROUP 'GRP_IODELAY0', but there is no IDELAYCTRL associated with this IODELAY_GROUP.
I have put this thread in many forums, but i didnot reply from any side. Please help me to resolve the issue.
Regards,
Mohsin