Logic Utilization View

The "View->Logic Utilization View" displays the hierarchical logic utilization of a design after the NCD is read with "Get logic utilization" checked. It also displays the total logic resources in the device and utilization % for each resource category. Click "+/-" in front of "Expand/Collapse all" to expand/collapse all hierarchies. Click "+/-" on each row to expand/collapse the hierarchy for that row.

The "Logic Utilization View" can be exported to an Excel spreadsheet (Excel->Show Logic Utilization in Excel function).

Spartan6 GCLK View in Excel

ADEPT v0.38.9 added a new function "Excel->Show Spartan6 GCLK in Excel" that displays GCLK pads, their pin numbers/signal names and BUFGs they can drive in an Excel spreadsheet. The snapshot is shown below. An example .xls file can be downloaded here.

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Virtex5 Component View

The Virtex5 Component View (View->Component View menu) has two parts:

The first part displays all DCM, PLL, BUFGCTRL and global clock pad (GC_P pins) in the order as they are on the device. It also highlights an important clocking rule (circled in the snapshot below) that the global clock pad can only drive BUFG/DCM/PLL in the same top or bottom half. The clocking components above the note are in the top half and the clock components below the note are in the bottom half.

The second part displays BUFIO, BUFR, DSP48, BRAMB, and RPMs used in the design when an NCD is read in (File->Read NCD File) wtih "Get Instance Names" checked (see the snapshot below):

The Component View can be exported to an Excel spreadsheet (Excel->Show Component in Excel menu). The placements of all instances can be exported to a UCF (File->Export Instance LOC to UCF).

Virtex6 DSP48 View

Compared to the Virtex5 DSP48 View in ADEPT, the Virtex6 DSP48 View has 5 new columns (circled in the snapshot below) for the new pre-adder in DSP48E1 slice. The INMODE4, INMODE3:0 and USE_DPORT columns display the actual values for the INMODE input and USE_DPORT attribute. The MULT_A and MULT_B columns display inputs to the multiplier A and B ports based on the decoding of INMODE and USE_DPORT.

Please check Virtex-6 FPGA DSP48E1 Slice User Guide for details on DSP48E1 operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

DSP48 View - Virtex5

ADEPT v0.38.6 added a new "View->DSP48 View" function for Virtex5. After an NCD is read with "Get DSP48 attributes" checked (see the snapshot at the end), the DSP48 view displays all DSP48 instances in the design with their placements (Comp Name column), OPMODE and ALUMODE values (OPMODE and ALUMODE columns) and their decodings (X, Y, Z and ALU OP columns), and pipeline register attributes (A/B/C/M/PREG columns). If OPMODE or ALUMODE are not connected to constant 1's or 0's, their values will have "?" in them. If OPMODE or ALUMODE can't be decoded, the corresponding decoding columns will be blank.

Please check Virtex-5 FPGA XtremeDSP Design Considerations User Guide for details on DSP48E operations. By the way, download Xilinx Document Navigator to manage all Xilinx documents.

Special Pin Setup Window

ADEPT 0.38.x has a new function "Tools->Special Pin Setup". This function displays information (tie high/low, types and important notes) for special purpose pins such as configuration pins, power pins, etc. A snapshot of this new function is shown below:

1. Pop-up window to select configuration mode, data width, configuration clk frequency and power supply ramp time.

• Review: display the special pin setup information for the selected mode/width
• Example: open the list of links for all configuration examples in your web browser
  
• Write UCF: write "PROHIBIT" constraints for dual-purpose pins to UCF
  

2. Current configuration mode/width, bitstream size, config clk frequency, power supply ramp time and total configuration time
3. Values of Mode pins M[2:0] for current configuration mode
4. Important notes on some configurations pins
5. Pins requiring special attention highlighted in red

Find IDELAYCTRL locations

ADEPT can be used to easily find IDELAYCTRLs in each IO column in a clock region. For Virtex5, Virtex6 or Virtex-7/Kintex-7, an IO column in a clock region is the same as an IO bank.

• Load the target device in ADEPT. The Pin table view is displayed.
• Run View->Display IDELAYCTRL, which shows the IDELAYCTRL_XmYn in the center of each IO column in a clock region.
• Run File->Read UCF to load pin locations. If any IO in an IO column of a clock region uses IDELAY or IODELAY in FIXED, VARIABLE, or VAR_LOADABLE mode, the IDELAYCTRL in that IO column/clock region needs to be used by manual instantiation or automatic replication in MAP.
• Optionally if a NCD is read in from File->Read NCD, the tool will display IDELAY or IODELAY modes in the Notes column for IOs using IDELAYs or IODELAYs and the instance names for all used IDELAYCTRLs.

Below is a snapshot of the GUI after an NCD is read in.Click on it to see the full image.

• The clock region XY is displayed in the first row of each clock region in the SLCR column.
• The Notes column shows the modes of IDELAY or IODELAY for all applicable IOs.
• IDELAYCTRL_XmYn is in the center of the clock region.
• IO bank number is shown in the Bank column. In this particular case, each IO bank is one clock region tall.

Virtex5 IO Bank View

The View->IO Bank View displays all IO banks in IO columns with  VCCO and DCI settings for each bank. v0.38.4 and newer also prints a warning message at the end of table that bitgen must be run with the .pcf file.

Depending on the device, there may be 3 or 4 IO columns displayed. The column header  indicates the IO column an IO bank is in:

• OL = Outer Left
• CL = Center Left
• CR = Center Right
• OR = Outer Right

The snapshot below shows the IO Bank View for a Virtex5 device.

Make Part Compatible

[Update May 21, 2011: click here for additional information about Make Part Compatible function for 7 Series FPGAs]
The "Tools->Make Part Compatible" function checks the pin compatibility between current selected part and a new device in the same package. The tool creates a spreadsheet that lists all pins from both parts side by side and highlights incompatible pins in red. The “PROHIBIT” column for all incompatible pins are set to yes (“Y”). Once the spreadsheet is reviewed, users can write out a UCF file with PROHIBIT constraints added for all incompatible user IOs.

Generate Orcad Symbol

ADEPT can export a CSV file that can be directly copied and pasted to Orcad Capture part generation spreadsheet to generate a multi-part symbol for the selected device.

Orcad 10.5 or newer is required because the "New Part from Spreadsheet" function was first added to version 10.5. For users with older versions of Orcad, the "Tools->Generate Part" function in Orcad should still work(http://www.orcad.com/documents/community.faqs/capture/cap03022.aspx) with simple changes to the CSV file exported in ADEPT.

1. Run ADEPT
2. Load target device
3. Run "File->Export CSV for Orcad Symbol" to export all pins (user I/Os, configuration pins, power pins, etc) to a csv file (say orcad_symbol.csv) that has the same columns as the Orcad symbol spreadsheet
4. Open the csv file orcad_symbol.csv in MS Excel. Scroll down to the last row and take note of the section number (the last column). The section number is the number of parts that will be generated for the device
5. Run Orcad Capture and select "New Part From Spreadsheet". On the "New Part Creation Spreadsheet" window, enter a part name in "Part Name" box, the section number above in the "No. of Sections" box, and select "Numeric" for "Part Numbering". This step MUST be done first for the section numbers to show up correctly for each pin.
6. Go back to MS Excel and select rows 7 to the last row and columns A to G. Press CTRL-C to copy the selection to clipboard.
7. Switch to Orcad Capture "New Part Creation Spreadsheet" window and select the first cell in the spreadsheet. Press CTRL-V to paste the clipboard content to the spreadsheet. Click "Save" to save the part. You now have a Orcad symbol with multiple parts: one part per bank (including bank 0 and MGT banks), one part for VCC*, one part for GND.